`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/10/23 12:57:04
// Design Name: 
// Module Name: control_unit
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////
`include "defines.vh"

module control_unit(
    input   logic [ 5: 0]       opcode1, //31:26
    input   logic [ 4: 0]       opcode2, //25:21
    input   logic [ 4: 0]       opcode3, //10:6
    input   logic [ 4: 0]       opcode4, //20:16
    input   logic [ 5: 0]       funct,   //5:0
    input   logic [`EXCS_BUS]   excs_i,
 
    output  logic               memtoreg,
    output  logic               memwrite,
    output  logic               branch,
    output  logic               alusrc,
    output  logic [ 1: 0]       regdst,
    output  logic               regwrite,
    output  logic               jump,
    output  logic [ 1: 0]       ext,
    output  logic [ 4: 0]       alucontrol,
    output  logic               mduen,

    //load&store store_select signal
    output  logic [ 3: 0]       store_sel,
    output  logic [ 3: 0]       load_type,

    //branch&jump
    output  logic [ 3: 0]       branch_type,
    output  logic               res_src,
    output  logic               pcsrc2,
    output  logic [`EXCS_BUS]   excs_o,
    output  logic               next_is_slot,
    input   logic               is_slot_i,
    output  logic               inslot
    );

    assign inslot = is_slot_i;

    logic instvalid;
    logic exc_sysc;
    logic exc_bp;
    logic exc_eret;

    always_comb begin
        excs_o              = excs_i;
        excs_o[`EXC_RI]     = !instvalid;
        excs_o[`EXC_SYSC]  = exc_sysc;
        excs_o[`EXC_BP]    = exc_bp;
        excs_o[`EXC_ERET]  = exc_eret;
    end

    always_comb begin

        alucontrol      = 5'b00000;
        memtoreg        = 1'b0;
        memwrite        = 1'b0;
        branch          = 1'b0;
        alusrc          = 1'b0;
        regdst          = 2'b00;
        regwrite        = 1'b0;
        jump            = 1'b0;
        ext             = 2'b00;
        mduen           = 1'b0;
        store_sel       = 4'b0;
        load_type       = 4'b0;
        branch_type     = 4'b0;
        res_src         = 1'b0;
        pcsrc2          = 1'b0;
        next_is_slot    = 1'b0;
        instvalid       = 1'b0;
        exc_sysc        = 1'b0;
        exc_bp          = 1'b0;
        exc_eret        = 1'b0;

        case(opcode1)  
            6'b010000:  begin
                case(opcode2)
                    5'b10000:   begin   //eret
                        exc_eret = 1'b1;
                        instvalid = 1'b1;
                    end
                    5'b00000:   begin   //mfc0
                        alucontrol = 5'b11001;
                        memtoreg = 1'b0;
                        memwrite = 1'b0;
                        branch = 1'b0;
                        alusrc = 1'b0;
                        regdst = 2'b00;
                        regwrite = 1'b1;
                        jump = 1'b0;
                        ext = 2'b00;
                        mduen = 1'b0;
                        res_src = 1'b0;
                        instvalid = 1'b1;
                    end
                    5'b00100:   begin   //mtc0
                        alucontrol = 5'b11010;
                        memtoreg = 1'b0;
                        memwrite = 1'b0;
                        branch = 1'b0;
                        alusrc = 1'b0;
                        regdst = 2'b00;
                        regwrite = 1'b0;
                        jump = 1'b0;
                        ext = 2'b00;
                        mduen = 1'b0;
                        res_src = 1'b0;
                        instvalid = 1'b1;
                    end
                endcase
            end
            6'b001000:  begin   //addi
                alucontrol = 5'b10111;
                memtoreg = 1'b0;
                memwrite = 1'b0;
                branch = 1'b0;
                alusrc = 1'b1;
                regdst = 2'b00;
                regwrite = 1'b1;
                jump = 1'b0;
                ext = 2'b01;
                mduen = 1'b0;
                res_src = 1'b0;
                instvalid = 1'b1;
            end

            6'b001001:  begin   //addiu
                alucontrol = 5'b10010;
                memtoreg = 1'b0;
                memwrite = 1'b0;
                branch = 1'b0;
                alusrc = 1'b1;
                regdst = 2'b00;
                regwrite = 1'b1;
                jump = 1'b0;
                ext = 2'b01;
                mduen = 1'b0;
                res_src = 1'b0;
                instvalid = 1'b1;
            end

            6'b001010:  begin   //slti
                alucontrol = 5'b00111;
                memtoreg = 1'b0;
                memwrite = 1'b0;
                branch = 1'b0;
                alusrc = 1'b1;
                regdst = 2'b00;
                regwrite = 1'b1;
                jump = 1'b0;
                ext = 2'b01;
                mduen = 1'b0;
                res_src = 1'b0;
                instvalid = 1'b1;
            end

            6'b001011:  begin   //sltiu
                alucontrol = 5'b01100;
                memtoreg = 1'b0;
                memwrite = 1'b0;
                branch = 1'b0;
                alusrc = 1'b1;
                regdst = 2'b00;
                regwrite = 1'b1;
                jump = 1'b0;
                ext = 2'b01;
                mduen = 1'b0;
                res_src = 1'b0;
                instvalid = 1'b1;
            end

            6'b001100:  begin   //andi
                alucontrol = 5'b00000;
                memtoreg = 1'b0;
                memwrite = 1'b0;
                branch = 1'b0;
                alusrc = 1'b1;
                regdst = 2'b00;
                regwrite = 1'b1;
                jump = 1'b0;
                ext = 2'b00;
                mduen = 1'b0;
                res_src = 1'b0;
                instvalid = 1'b1;
            end

            6'b001101:  begin   //ori
                alucontrol = 5'b00001;
                memtoreg = 1'b0;
                memwrite = 1'b0;
                branch = 1'b0;
                alusrc = 1'b1;
                regdst = 2'b00;
                regwrite = 1'b1;
                jump = 1'b0;
                ext = 2'b00;
                mduen = 1'b0;
                res_src = 1'b0;
                instvalid = 1'b1;
            end

            6'b001110:  begin   //xori
                alucontrol = 5'b00011;
                memtoreg = 1'b0;
                memwrite = 1'b0;
                branch = 1'b0;
                alusrc = 1'b1;
                regdst = 2'b00;
                regwrite = 1'b1;
                jump = 1'b0;
                ext = 2'b00;
                mduen = 1'b0;
                res_src = 1'b0;
                instvalid = 1'b1;
            end

            6'b001111:  begin   //lui
                alucontrol = 5'b00001;
                memtoreg = 1'b0;
                memwrite = 1'b0;
                branch = 1'b0;
                alusrc = 1'b1;
                regdst = 2'b00;
                regwrite = 1'b1;
                jump = 1'b0;
                ext = 2'b10;
                mduen = 1'b0;
                res_src = 1'b0;
                instvalid = 1'b1;
            end

            //---load&store--------------------------------------------------------
            6'b100000:  begin   //lb
                alucontrol = 5'b00010;
                memtoreg = 1'b1;
                memwrite = 1'b0;
                branch = 1'b0;
                alusrc = 1'b1;
                regdst = 2'b00;
                regwrite = 1'b1;
                jump = 1'b0;
                ext = 2'b01;
                mduen = 1'b0;
                store_sel = 4'b0000;
                load_type = 4'b0000;
                res_src = 1'b0;
                //mem_en = 1'b1;
                instvalid = 1'b1;
            end

            6'b100100:  begin   //lbu
                alucontrol = 5'b00010;
                memtoreg = 1'b1;
                memwrite = 1'b0;
                branch = 1'b0;
                alusrc = 1'b1;
                regdst = 2'b00;
                regwrite = 1'b1;
                jump = 1'b0;
                ext = 2'b01;
                mduen = 1'b0;
                store_sel = 4'b0000;
                load_type = 4'b0001;
                res_src = 1'b0;
                //mem_en = 1'b1;
                instvalid = 1'b1;
            end
            
            6'b100001:  begin   //lh
                alucontrol = 5'b00010;
                memtoreg = 1'b1;
                memwrite = 1'b0;
                branch = 1'b0;
                alusrc = 1'b1;
                regdst = 2'b00;
                regwrite = 1'b1;
                jump = 1'b0;
                ext = 2'b01;
                mduen = 1'b0;
                store_sel = 4'b0000;
                load_type = 4'b0010;
                res_src = 1'b0;
                //mem_en = 1'b1;
                instvalid = 1'b1;
            end

            6'b100101:  begin   //lhu
                alucontrol = 5'b00010;
                memtoreg = 1'b1;
                memwrite = 1'b0;
                branch = 1'b0;
                alusrc = 1'b1;
                regdst = 2'b00;
                regwrite = 1'b1;
                jump = 1'b0;
                ext = 2'b01;
                mduen = 1'b0;
                store_sel = 4'b0000;
                load_type = 4'b0011;
                res_src = 1'b0;
                //mem_en = 1'b1;
                instvalid = 1'b1;
            end

            6'b100011:  begin   //lw
                alucontrol = 5'b00010;
                memtoreg = 1'b1;
                memwrite = 1'b0;
                branch = 1'b0;
                alusrc = 1'b1;
                regdst = 2'b00;
                regwrite = 1'b1;
                jump = 1'b0;
                ext = 2'b01;
                mduen = 1'b0;
                store_sel = 4'b0000;
                load_type = 4'b0100;
                res_src = 1'b0;
                //mem_en = 1'b1;
                instvalid = 1'b1;
            end

            6'b101000:  begin   //sb
                alucontrol = 5'b00010;
                memtoreg = 1'b0;
                memwrite = 1'b1;
                branch = 1'b0;
                alusrc = 1'b1;
                regdst = 2'b00;
                regwrite = 1'b0;
                jump = 1'b0;
                ext = 2'b01;
                mduen = 1'b0;
                store_sel = 4'b0001;
                res_src = 1'b0;
                //mem_en = 1'b1;
                instvalid = 1'b1;
            end

            6'b101001:  begin   //sh
                alucontrol = 5'b00010;
                memtoreg = 1'b0;
                memwrite = 1'b1;
                branch = 1'b0;
                alusrc = 1'b1;
                regdst = 2'b00;
                regwrite = 1'b0;
                jump = 1'b0;
                ext = 2'b01;
                mduen = 1'b0;
                store_sel = 4'b0011;
                res_src = 1'b0;
                //mem_en = 1'b1;
                instvalid = 1'b1;
            end

            6'b101011:  begin    //sw
                alucontrol = 5'b00010;
                memtoreg = 1'b0;
                memwrite = 1'b1;
                branch = 1'b0;
                alusrc = 1'b1;
                regdst = 2'b00;
                regwrite = 1'b0;
                jump = 1'b0;
                ext = 2'b01;
                mduen = 1'b0;
                store_sel = 4'b1111;
                res_src = 1'b0;
                //mem_en = 1'b1;
                instvalid = 1'b1;
            end
            //---load&store ends---------------------------------------------------

            6'b000000: begin    
                case(funct)
                    6'b001100:  begin   //syscall
                        exc_sysc = 1'b1;
                        instvalid = 1'b1;
                    end

                    6'b001101:  begin   //break
                        exc_bp = 1'b1;
                        instvalid = 1'b1;
                    end

                    6'b001000:  begin   //jr
                        memtoreg = 1'b0;
                        memwrite = 1'b0;
                        branch = 1'b0;
                        alusrc = 1'b0;
                        regdst = 2'b00;
                        regwrite = 1'b0;
                        jump = 1'b1;
                        ext = 2'b01;
                        mduen = 1'b0;
                        res_src = 1'b0;
                        pcsrc2 = 1'b1;
                        instvalid = 1'b1;
                        next_is_slot = 1'b1;
                    end

                    6'b001001:  begin   //jalr
                        memtoreg = 1'b0;
                        memwrite = 1'b0;
                        branch = 1'b0;
                        alusrc = 1'b0;
                        regdst = 2'b01;
                        regwrite = 1'b1;
                        jump = 1'b1;
                        ext = 2'b01;
                        mduen = 1'b0;
                        res_src = 1'b1;
                        pcsrc2 = 1'b1;
                        instvalid = 1'b1;
                        next_is_slot = 1'b1;
                    end

                    6'b011000:  begin  //mult
                        alucontrol = 5'b11111;
                        memtoreg = 1'b0;
                        memwrite = 1'b0;
                        branch = 1'b0;
                        alusrc = 1'b0;
                        regdst = 2'b00;
                        regwrite = 1'b0;
                        jump = 1'b0;
                        ext = 2'b00;
                        mduen = 1'b1;
                        res_src = 1'b0;
                        instvalid = 1'b1;
                    end

                    6'b011001:  begin  //multu
                        alucontrol = 5'b11110;
                        memtoreg = 1'b0;
                        memwrite = 1'b0;
                        branch = 1'b0;
                        alusrc = 1'b0;
                        regdst = 2'b00;
                        regwrite = 1'b0;
                        jump = 1'b0;
                        ext = 2'b00;
                        mduen = 1'b1;
                        res_src = 1'b0;
                        instvalid = 1'b1;
                    end

                    6'b011010:  begin  //div
                        alucontrol = 5'b11101;
                        memtoreg = 1'b0;
                        memwrite = 1'b0;
                        branch = 1'b0;
                        alusrc = 1'b0;
                        regdst = 2'b00;
                        regwrite = 1'b0;
                        jump = 1'b0;
                        ext = 2'b00;
                        mduen = 1'b1;
                        res_src = 1'b0;
                        instvalid = 1'b1;
                    end

                    6'b011011:  begin  //divu
                        alucontrol = 5'b11100;
                        memtoreg = 1'b0;
                        memwrite = 1'b0;
                        branch = 1'b0;
                        alusrc = 1'b0;
                        regdst = 2'b00;
                        regwrite = 1'b0;
                        jump = 1'b0;
                        ext = 2'b00;
                        mduen = 1'b1;
                        res_src = 1'b0;
                        instvalid = 1'b1;
                    end

                    6'b000000:  begin  //sll
                        alucontrol = 5'b01101;
                        memtoreg = 1'b0;
                        memwrite = 1'b0;
                        branch = 1'b0;
                        alusrc = 1'b0;
                        regdst = 2'b01;
                        regwrite = 1'b1;
                        jump = 1'b0;
                        ext = 2'b00;
                        mduen = 1'b0;
                        res_src = 1'b0;
                        instvalid = 1'b1;
                    end

                    6'b000010:  begin   //srl
                        alucontrol = 5'b01110;
                        memtoreg = 1'b0;
                        memwrite = 1'b0;
                        branch = 1'b0;
                        alusrc = 1'b0;
                        regdst = 2'b01;
                        regwrite = 1'b1;
                        jump = 1'b0;
                        ext = 2'b00;
                        mduen = 1'b0;
                        res_src = 1'b0;
                        instvalid = 1'b1;
                    end

                    6'b000011:  begin  //sra
                        alucontrol = 5'b01111;
                        memtoreg = 1'b0;
                        memwrite = 1'b0;
                        branch = 1'b0;
                        alusrc = 1'b0;
                        regdst = 2'b01;
                        regwrite = 1'b1;
                        jump = 1'b0;
                        ext = 2'b00;  
                        mduen = 1'b0;
                        res_src = 1'b0;
                        instvalid = 1'b1;
                    end 

                    6'b100000:  begin  //add
                        alucontrol = 5'b10111;
                        memtoreg = 1'b0;
                        memwrite = 1'b0;
                        branch = 1'b0;
                        alusrc = 1'b0;
                        regdst = 2'b01;
                        regwrite = 1'b1;
                        jump = 1'b0;
                        ext = 2'b00;
                        mduen = 1'b0;
                        res_src = 1'b0;
                        instvalid = 1'b1;
                    end

                    6'b100001:  begin  //addu
                        alucontrol = 5'b10010;
                        memtoreg = 1'b0;
                        memwrite = 1'b0;
                        branch = 1'b0;
                        alusrc = 1'b0;
                        regdst = 2'b01;
                        regwrite = 1'b1;
                        jump = 1'b0;
                        ext = 2'b00;
                        mduen = 1'b0;
                        res_src = 1'b0;
                        instvalid = 1'b1;
                    end

                    6'b100010:  begin  //sub
                        alucontrol = 5'b00110;
                        memtoreg = 1'b0;
                        memwrite = 1'b0;
                        branch = 1'b0;
                        alusrc = 1'b0;
                        regdst = 2'b01;
                        regwrite = 1'b1;
                        jump = 1'b0;
                        ext = 2'b00;
                        mduen = 1'b0;
                        res_src = 1'b0;
                        instvalid = 1'b1;
                    end

                    6'b100011:  begin  //subu
                        alucontrol = 5'b10011;
                        memtoreg = 1'b0;
                        memwrite = 1'b0;
                        branch = 1'b0;
                        alusrc = 1'b0;
                        regdst = 2'b01;
                        regwrite = 1'b1;
                        jump = 1'b0;
                        ext = 2'b00;
                        mduen = 1'b0;
                        res_src = 1'b0;
                        instvalid = 1'b1;
                    end

                    6'b101010:  begin  //slt
                        alucontrol = 5'b00111;
                        memtoreg = 1'b0;
                        memwrite = 1'b0;
                        branch = 1'b0;
                        alusrc = 1'b0;
                        regdst = 2'b01;
                        regwrite = 1'b1;
                        jump = 1'b0;
                        ext = 2'b00;
                        mduen = 1'b0;
                        res_src = 1'b0;
                        instvalid = 1'b1;
                    end

                    6'b101011:  begin  //sltu
                        alucontrol = 5'b01100;
                        memtoreg = 1'b0;
                        memwrite = 1'b0;
                        branch = 1'b0;
                        alusrc = 1'b0;
                        regdst = 2'b01;
                        regwrite = 1'b1;
                        jump = 1'b0;
                        ext = 2'b00;
                        mduen = 1'b0;
                        res_src = 1'b0;
                        instvalid = 1'b1;
                    end

                    6'b100100:  begin  //and
                        alucontrol = 5'b00000;
                        memtoreg = 1'b0;
                        memwrite = 1'b0;
                        branch = 1'b0;
                        alusrc = 1'b0;
                        regdst = 2'b01;
                        regwrite = 1'b1;
                        jump = 1'b0;
                        ext = 2'b00;
                        mduen = 1'b0;
                        res_src = 1'b0;
                        instvalid = 1'b1;
                    end

                    6'b100101:  begin  //or
                        alucontrol = 5'b00001;
                        memtoreg = 1'b0;
                        memwrite = 1'b0;
                        branch = 1'b0;
                        alusrc = 1'b0;
                        regdst = 2'b01;
                        regwrite = 1'b1;
                        jump = 1'b0;
                        ext = 2'b00;
                        mduen = 1'b0;
                        res_src = 1'b0;
                        instvalid = 1'b1;
                    end

                    6'b100110:  begin  //xor
                        alucontrol = 5'b00011;
                        memtoreg = 1'b0;
                        memwrite = 1'b0;
                        branch = 1'b0;
                        alusrc = 1'b0;
                        regdst = 2'b01;
                        regwrite = 1'b1;
                        jump = 1'b0;
                        ext = 2'b00;
                        mduen = 1'b0;
                        res_src = 1'b0;
                        instvalid = 1'b1;
                    end

                    6'b100111:  begin  //nor
                        alucontrol = 5'b00100;
                        memtoreg = 1'b0;
                        memwrite = 1'b0;
                         branch = 1'b0;
                        alusrc = 1'b0;
                        regdst = 2'b01;
                        regwrite = 1'b1;
                        jump = 1'b0;
                        ext = 2'b00;
                        mduen = 1'b0;
                        res_src = 1'b0;
                        instvalid = 1'b1;
                    end

                    6'b000100:  begin  //sllv
                        alucontrol = 5'b00101;
                        memtoreg = 1'b0;
                        memwrite = 1'b0;
                        branch = 1'b0;
                        alusrc = 1'b0;
                        regdst = 2'b01;
                        regwrite = 1'b1;
                        jump = 1'b0;
                        ext = 2'b00;
                        mduen = 1'b0;
                        res_src = 1'b0;
                        instvalid = 1'b1;
                    end

                    6'b000110:  begin  //srlv
                        alucontrol = 5'b01001;
                        memtoreg = 1'b0;
                        memwrite = 1'b0;
                        branch = 1'b0;
                        alusrc = 1'b0;
                        regdst = 2'b01;
                        regwrite = 1'b1;
                        jump = 1'b0;
                        ext = 2'b00;
                        mduen = 1'b0;
                        res_src = 1'b0;
                        instvalid = 1'b1;
                    end

                    6'b000111:  begin  //srav
                        alucontrol = 5'b01000;
                        memtoreg = 1'b0;
                        memwrite = 1'b0;
                        branch = 1'b0;
                        alusrc = 1'b0;
                        regdst = 2'b01;
                        regwrite = 1'b1;
                        jump = 1'b0;
                        ext = 2'b00;
                        mduen = 1'b0;
                        res_src = 1'b0;
                        instvalid = 1'b1;
                    end

                    6'b010001:  begin  //mthi
                        alucontrol = 5'b01010;
                        memtoreg = 1'b0;
                        memwrite = 1'b0;
                        branch = 1'b0;
                        alusrc = 1'b0;
                        regdst = 2'b00;
                        regwrite = 1'b0;
                        jump = 1'b0;
                        ext = 2'b00;
                        mduen = 1'b0;
                        res_src = 1'b0;
                        instvalid = 1'b1;
                    end

                    6'b010011:  begin  //mtlo
                        alucontrol = 5'b01011;
                        memtoreg = 1'b0;
                        memwrite = 1'b0;
                        branch = 1'b0;
                        alusrc = 1'b0;
                        regdst = 2'b01;
                        regwrite = 1'b1;
                        jump = 1'b0;
                        ext = 2'b00;
                        mduen = 1'b0;
                        res_src = 1'b0;
                        instvalid = 1'b1;
                    end

                    6'b010000:  begin  //mfhi
                        alucontrol = 5'b10000;
                        memtoreg = 1'b0;
                        memwrite = 1'b0;
                        branch = 1'b0;
                        alusrc = 1'b0;
                        regdst = 2'b01;
                        regwrite = 1'b1;
                        jump = 1'b0;
                        ext = 2'b00;
                        mduen = 1'b0;
                        res_src = 1'b0;
                        instvalid = 1'b1;
                    end

                    6'b010010:  begin  //mflo
                        alucontrol = 5'b10001;
                        memtoreg = 1'b0;
                        memwrite = 1'b0;
                        branch = 1'b0;
                        alusrc = 1'b0;
                        regdst = 2'b01;
                        regwrite = 1'b1;
                        jump = 1'b0;
                        ext = 2'b00;
                        mduen = 1'b0;
                        res_src = 1'b0;
                        instvalid = 1'b1;
                    end
                endcase
            end
            
            //---branch&jump-------------------------------------------------------
            6'b000100: begin    //beq
                memtoreg = 1'b0;
                memwrite = 1'b0;
                branch = 1'b1;
                alusrc = 1'b0;
                regdst = 2'b00;
                regwrite = 1'b0;
                jump = 1'b0;
                ext = 2'b01;
                mduen = 1'b0;
                branch_type = 4'b0000;
                res_src = 1'b0;
                instvalid = 1'b1;
                next_is_slot = 1'b1;
            end
            
            6'b000101: begin    //bne
                memtoreg = 1'b0;
                memwrite = 1'b0;
                branch = 1'b1;
                alusrc = 1'b0;
                regdst = 2'b00;
                regwrite = 1'b0;
                jump = 1'b0;
                ext = 2'b01;
                mduen = 1'b0;
                branch_type = 4'b0001;
                res_src = 1'b0;
                instvalid = 1'b1;
                next_is_slot = 1'b1;
            end

            6'b000001: begin    //bgez、bltz、bgezal、bltzal
                case(opcode4)
                    5'b00001:   begin   //bgez
                        memtoreg = 1'b0;
                        memwrite = 1'b0;
                        branch = 1'b1;
                        alusrc = 1'b0;
                        regdst = 2'b00;
                        regwrite = 1'b0;
                        jump = 1'b0;
                        ext = 2'b01;
                        mduen = 1'b0;
                        branch_type = 4'b0010;
                        res_src = 1'b0;
                        instvalid = 1'b1;
                        next_is_slot = 1'b1;
                    end
                    5'b00000:   begin   //bltz
                        memtoreg = 1'b0;
                        memwrite = 1'b0;
                        branch = 1'b1;
                        alusrc = 1'b0;
                        regdst = 2'b00;
                        regwrite = 1'b0;
                        jump = 1'b0;
                        ext = 2'b01;
                        mduen = 1'b0;
                        branch_type = 4'b0011;
                        res_src = 1'b0;
                        instvalid = 1'b1;
                        next_is_slot = 1'b1;
                    end
                    5'b10001:   begin   //bgezal
                        memtoreg = 1'b0;
                        memwrite = 1'b0;
                        branch = 1'b1;
                        alusrc = 1'b0;
                        regdst = 2'b10;
                        regwrite = 1'b1;
                        jump = 1'b0;
                        ext = 2'b01;
                        mduen = 1'b0;
                        branch_type = 4'b0100;
                        res_src = 1'b1;
                        instvalid = 1'b1;
                        next_is_slot = 1'b1;
                    end
                    5'b10000:   begin   //bltzal
                        memtoreg = 1'b0;
                        memwrite = 1'b0;
                        branch = 1'b1;
                        alusrc = 1'b0;
                        regdst = 2'b10;
                        regwrite = 1'b1;
                        jump = 1'b0;
                        ext = 2'b01;
                        mduen = 1'b0;
                        branch_type = 4'b0101;
                        res_src = 1'b1;
                        instvalid = 1'b1;
                        next_is_slot = 1'b1;
                    end
                endcase
            end

            6'b000111: begin    //bgtz
                memtoreg = 1'b0;
                memwrite = 1'b0;
                branch = 1'b1;
                alusrc = 1'b0;
                regdst = 2'b00;
                regwrite = 1'b0;
                jump = 1'b0;
                ext = 2'b01;
                mduen = 1'b0;
                branch_type = 4'b0110;
                res_src = 1'b1;
                instvalid = 1'b1;
                next_is_slot = 1'b1;
            end

            6'b000110: begin    //blez
                memtoreg = 1'b0;
                memwrite = 1'b0;
                branch = 1'b1;
                alusrc = 1'b0;
                regdst = 2'b00;
                regwrite = 1'b0;
                jump = 1'b0;
                ext = 2'b01;
                mduen = 1'b0;
                branch_type = 4'b0111;
                res_src = 1'b1;
                instvalid = 1'b1;
                next_is_slot = 1'b1;
            end

            6'b000010: begin    //j
                memtoreg = 1'b0;
                memwrite = 1'b0;
                branch = 1'b0;
                alusrc = 1'b0;
                regdst = 2'b00;
                regwrite = 1'b0;
                jump = 1'b1;
                ext = 2'b01;
                mduen = 1'b0;
                res_src = 1'b0;
                instvalid = 1'b1;
                next_is_slot = 1'b1;
            end

            6'b000011: begin    //jal
                memtoreg = 1'b0;
                memwrite = 1'b0;
                branch = 1'b0;
                alusrc = 1'b0;
                regdst = 2'b10;
                regwrite = 1'b1;
                jump = 1'b1;
                ext = 2'b01;
                mduen = 1'b0;
                res_src = 1'b1;
                instvalid = 1'b1;
                next_is_slot = 1'b1;
            end

            //---branch&jump end---------------------------------------------------
        endcase
    end

endmodule
